The present invention relates to electronic circuits and operating methods, and more particularly, to delay locked loops and delay locking methods using the same.
A delay locked loop may be used to provide a clock signal having a predetermined phase shift with respect to a reference clock signal. Even though the clock signal supplied by the delay locked loop is shifted with respect to the reference clock, the phase is earlier than the reference clock. The signal generated by the delay locked loop will be referred to herein as an advanced clock signal.
Generally, an advanced clock signal may be used in an integrated circuit (IC) having relatively high integration, such as a Merged Memory with Logic (MML), a Rambus DRAM (RDRAM), and a Double Data Rate Synchronous DRAM (DDR). The reference clock signal is input at an input pin to be distributed throughout the entire device. The reference clock signal arriving at a position relatively far from the input pin may be more delayed with respect to the reference clock signal at a position adjacent to the input pin. Due to the delay difference, it may be difficult to maintain synchronization of each portion of the IC.
Thus, the delay locked loop may be included in the IC. The delay locked loop generally is located near an input pin that receives a reference clock signal. The delay locked loop receives the reference clock signal, and generates an advanced clock signal. The advanced clock signal is similar to the reference clock signal in frequency and length. However, the advanced clock signal is advanced against the reference clock signal by a phase corresponding to the delay time from the near position to the far position with reference to the input pin that receives the reference clock signal. The reference clock signal is used near the input pin of the reference clock signal, and the advanced reference clock signal is transferred to circuits far from the input pin. In this manner, a synchronized clock signal may be received in all parts of the IC, and the synchronized signal can allow the IC to operate in synchronism with the reference clock signal even at a very high speed.
FIG. 1 is a schematic block diagram of a conventional delay locked loop. The conventional delay locked loop 10 includes an input buffer 12, a variable delay circuit 14, a phase sensing pump 16 and a delay compensation circuit 18. The input buffer 12 buffers an external clock signal ECLK1 to supply a reference clock signal RCLK1.
The delay locked loop controls the delay time according to the variable delay circuit 14 so that the phase of the feedback clock signal FCLK1 coincides with the phase of the reference clock signal RCLK1. Other delay locked loops are described in U.S. Pat. Nos. 5,614,855; 5,642,082 and 5,875,219.
The variable delay circuit of the conventional delay locked loop includes n delay terminals, where n indicates a predetermined number. A variable delay range is defined by the predetermined number of delay terminals, which may restrict the operational frequency. That is, when a frequency lower than the operational frequency region is input, the phase shift of the variable delay circuit may not be increased, so that the jitter may be generated in the direction of the feedback signal earlier than the external pin signal. Also, when a frequency higher than the operational frequency region is input, the phase shift of the variable delay circuit may not be reduced, so that the jitter may be generated in the direction of the feedback signal later than the external input signal. Thus, the operational frequency of the IC may be defined by the delay locked loop.
It is an object of the present invention to provide delay locked loops and methods that can have an increased operational frequency region.
It is another object of the present invention to provide delay locked loops and methods that can match the phase of the feedback clock signal with that of the reference clock signal using the delay locked loop.
These and other objects may be provided, according to the present invention, by delay locked loops that generate an advanced clock signal that is synchronized with a received reference clock signal. The delay locked loops may comprise a phase sensing pump that senses a phase difference between feedback signals related to the advanced clock signal with respect to the reference clock signal, to supply a control signal controlling a voltage level in accordance with the direction of the phase difference. A variable delay circuit delays the reference clock signal, corresponding to the voltage level of the control signal supplied from the phase sensing pump. A phase shifter compares the phase of the reference clock signal with the phase of a delayed clock signal delayed by the variable delay circuit, to generate the advanced clock signal. The advanced clock signal is generated by shifting the delayed clock signal by the reference phase value, when a phase difference of the delayed clock signal with respect to the reference clock signal is more than a reference phase value, and is generated without shifting the phase, when a phase difference of the delayed clock signal with respect to the reference clock signal is less than the reference phase value.
According to another aspect of the present invention, delay locked loops that generate an advanced clock signal synchronized with a reference clock signal, may comprise a phase sensing pump that senses a phase difference between feedback signals related to the phase of the advanced clock signal with respect to the phase of the reference clock signal, and supplies a control signal controlling a voltage level in accordance with the direction of the phase difference. A variable delay circuit includes multiple delay terminals that delay the reference clock signal to generate the advanced clock signal, in response to the voltage level of the control signal supplied from the phase sensing pump. The number of delay terminals included in the variable delay circuit is controlled by the quantity of the phase difference of the feedback clock signal with respect to the reference signal.
According to still another aspect of the present invention, delay locked loops that generate an advanced clock signal synchronized with a reference clock signal, may comprise a phase sensing pump that senses a phase difference between feedback signals related to the phase of the advanced clock signal with respect to the reference clock signal, and supplies a control signal that controls a voltage level in accordance with the direction of the phase difference. A variable delay circuit including multiple delay terminals, delays the reference clock signal, corresponding to the voltage level of the control signal supplied from the phase sensing pump, to generate the advanced clock signal. The number of the activated delay terminals of the variable delay circuit preferably is controlled by a frequency of the reference clock signal.
Delay lock methods according to the invention can use a delay locked loop that generates an advanced clock signal synchronized with a reference clock signal. Delay lock methods using a delay locked loop to generate an advanced clock signal synchronized with a reference clock signal, may comprise the steps of a) delaying the reference clock signal to generate a delayed clock signal; b) sensing a phase difference of the delayed clock signal with respect to the reference clock signal; c) determining whether the phase difference is more than a predetermined reference phase value; d) shifting the phase of the delayed clock signal when the phase difference is more than the reference phase value to generate the advanced clock signal; and e) controlling the amount of delay in the reference clock signal in step a).
According to another method aspect, delay lock methods for a variable delay circuit generating an advanced clock signal synchronized with a received reference clock signal, and the reference clock signal as multiple delay terminals, may comprise: a) sensing a phase difference between feedback signals related to a phase of the advanced clock signal with respect to the reference clock signal; b) inverting the phase of the feedback signal when the phase difference is more than Π; c) controlling the number of an activated delay terminals of the variable delay circuit, in response to a width of the phase difference; and d) delaying the reference clock signal by the delay time varied in response to the direction of the phase difference, to generate the advanced clock signal.
According to delay locked loops and delay lock methods of the present invention, the operational frequency region can be increased. Also, excessive time need not be used for synchronizing the advanced clock signal ICLK2 with the reference clock signal RCLK2.